1. Field of the Invention
The invention pertains to the field of non-volatile memory cells. In particular, the present invention relates to non-volatile memory cells having a high coupling ratio.
2. Description of the Related Art
Charge retention, namely the ability of memory devices to maintain a charge stored therein, is a major concern of semiconductor devices manufacturers. Charge retention is of particular importance to non-volatile storage devices, as their designed retention time is now measured in terms of years and even decades. One of the causes of decreased charge retention is believed to be leakage, in which charges stored within nitride traps or on a floating gate leak away by, for example, tunneling through a thin oxide layer. This undesirable leakage may even occur without the presence of erase voltage. As the charges leak away, the informational content of the cell may become ambiguous and data may be lost.
One way to decrease the effects of this leakage is to increase the stored charge and to increase the coupling ratio of the device. A high coupling ratio helps to decrease the high voltage required for programming and erasing the memory cell. For this purpose, it is desirable to increase the surface area available for capacitive coupling, the charge storage mechanism for memory non-volatile memory cells. For floating gate memory cells, the charge is typically stored on a gate that is separated from the channel by a thin oxide layer called a tunnel oxide layer, through which charge carriers migrate via Fowler-Nordheim tunneling. Another gate layer is situated above the floating gate layer, and is called the control gate. The floating gate is isolated from the control gate by an interpolysilicon dielectric layer.
FIG. 1 is a cross sectional view of a one transistor (hereafter 1T) non-volatile memory cell, taken along the bit line direction. Reference numeral 180 represents the bitline contact and reference numeral 170 represents the Vss contact. As the structures of interest here reside above the substrate, a representation of the substrate and associated implant regions has been omitted from FIG. 1 for the sake of brevity. A thin oxide layer 110 separates the floating gate layer (hereafter FG layer) 120 from the underlying channel region of the substrate. This thin oxide layer 110 is typically about 100 .ANG. microns in thickness, and allows for Fowler-Nordheim tunneling as a means of programming and erasing. Between the control gate (hereafter CG) layer 140 and the FG layer 120 is a dielectric layer 130. Finally, sidewall spacers 150 provide the necessary isolation and protection of the FG and CG layers 120 and 140, respectively.
FIG. 2 is a cross sectional view of the non-volatile memory cell of FIG. 1, taken along the wordline direction. Field isolation oxide structures 260 separate the transistors from one another. The tunneling oxide 110 separates the FG layer 120 from the underlying substrate. The dielectric layer 130 separates the FG layer 120 from the CG layer 140. The CG layer 140 is common among the transistors of a same row, and acts as a wordline of the array. In order to increase the coupling capacitance between the CG layer 140 and the FG layer 120, the FG layer 120 and its overlying dielectric layer 130 are extended past the boundaries of the tunnel oxide 110 to form so-called wings 290. The wings 290 provide additional surface area on which the charges migrating across the tunneling oxide 110 may accumulate. These wings 290 allow the memory cell to have an increased coupling ratio and a lower voltage to be used for both programming and erase functions. The wings increase the total charge that may be stored by the FG layer 120, but they decrease the number of transistors that may be fitted onto a wordline of a given width. Indeed, due to the presence and width of the wings 290, the width of each such non-volatile memory cell is much greater than the minimum Field Oxide Mask (hereafter FOM) width. The FOM is an isolation mask structure (generally the LOCOS isolation oxide) and defines the device width by separating the active regions of adjacent devices. The CG 140 contacts the field oxide isolation structures 260 at the wordline sidewall surfaces 295. Therefore, charge carriers may accumulate on the FG layer 120 along the wordline sidewall surfaces 295, along the wings 290 and over the tunneling oxide 110. In other words, the charge carriers may accumulate over an area corresponding to the surface area of the dielectric layer 130. The greater this surface area, the greater the capacitance and the greater the coupling ratio.
FIG. 5 shows a schematic representation of the CG layer 140, and the manner in which it overlaps the FG layer 120. The orientation of the CG layer 140 is shown by the arrows adjacent the illustrated structure. Indeed, the active area, the wings and the WL (wordline) sidewalls are aligned in the wordline direction, corresponding to the plane of the paper in FIG. 2. The orientation of the WL sidewalls themselves, however, is along the bitline direction, i.e., into and out of the plane of the paper in FIG. 2. As shown in FIG. 5, the CG layer 140 overlaps the FG layer 120 over the active area, corresponding to the width of the tunneling oxide 110 over the induced channel, over the wings 290, and over the wordline sidewalls 295 (denoted by the legend WL sidewall in FIG. 5). Typically, the active area and the wings 290 have a width of about 0.35 .mu.m, whereas the height of the WL sidewalls is about 0.2 .mu.m. Capacitance is proportional to the area onto which charges may accumulate divided by the thickness of the intervening dielectric. In a stacked double polysilicon structure, such as shown in FIG. 1, wherein the polysilicon layers are separated from one another by a dielectric layer and wherein the floating gate layer is separated from the underlying substrate by a tunnel oxide, the capacitance ratio C.R. of the structure is generally defined by the expression: ##EQU1## where C.sub.dielectric is the capacitance formed by the control and floating gate layers and C.sub.tunnel is the capacitance between the substrate and the floating gate layer. Assuming that the ratio of thickness' of the dielectric and tunnel layers is about 2.2, the capacitance ratio for the structure shown in FIG. 1 is about: ##EQU2##
This results in a coupling ratio of about 0.65 for the structure shown in FIG. 1.
The structure shown in FIGS. 1 and 2, however, is not completely satisfactory, for at least the following reasons. At the outset, it is apparent that the width of the device is greatly affected by the size of the wings. To maintain a high coupling ratio in the face of shrinking device dimensions, the wide wings 290 shown in FIG. 2 are required. Wings of large size, by increasing the width of the device, necessarily reduce the number of such transistors that can be fitted along a wordline of a given size. Reducing the width of the wings 290 would allow a greater number of such devices to fit across a given wordline, but the ability of the FG layer 120 to store charge would be proportionally reduced.
In an effort to address this problem, Shallow Trench Isolation (SA-STI) structures have been proposed to reduce the width of the cell without decreasing the capacitive coupling between the floating and control gates. On representative example of such an approach is shown in K. Sakui et al., NAND Flash Memory Technology and Future Direction, presented at the 15.sup.th Annual IEEE Non-Volatile Semiconductor Memory Workshop, Monterey, Calif. Feb. 9-12, 1997. In Sakui et al., a Self-Aligned Shallow Trench Isolation (SA-STI) technology is utilized to separate neighboring bits, instead of a field oxide or LOCOS structures. The shallow trench structure allows Sakui et al to eliminate wing structures in favor of a structure wherein the control gate is extended to cover the sidewalls of the floating gate, again in the general fashion shown in FIG. 5. This increases the coupling ratio of the device, even through the wing structures have been eliminated. However, SA-STI structures require complex processing, and the sidewalls of the trench structures are highly susceptible to performance degrading contamination from impurities such as reactive mobile ions and the like.
Moreover, SA-STI structures are not readily or economically incorporated into other devices, such as SRAM structures. Indeed, to incorporate non-volatile memory structures into SRAM arrays, for example, it is generally accepted that the extra processing steps and cost necessitated thereby should be kept to a minimum, typically not to exceed 20% of the process steps and costs of a SRAM array alone.
What is needed, therefore, is a memory cell of small dimensions that maintains a high coupling ratio. What is also needed is a non-volatile memory cell having a high coupling ratio and improved charge retention characteristics. What is also needed is a non-volatile memory that is readily incorporated into other technologies, such as SRAM technology. What is also needed is a memory cell, the formation of which does not necessitate an unacceptable number of processing steps that are not shared with other MOS structures.